1. Background Art
With reference to Japanese unexamined patent application publication No. 1995-37396 (Patent Document I), a word line Xi is activated by a drive device 280, and a predecoder (not shown) outputs a decoded predecode signal VA to the drive device 280 (FIG. 10). The drive device 280 is provided with two P-channel transistors 780, 800 connected between a multiplexed signal MUXi and ground. A gate of the P-channel transistor 780 is connected to VA. A gate of the P-channel transistor 800 is connected to a fixed voltage VN. A node 810 is connected to the word line Xi associated with the drive device 280 and to a negative charge pump circuit 320. When a negative bias is applied to the word line Xi, the level of VA is rendered high, thereby preventing the negative bias from leaking through the P-channel transistor 780.
2. Problems to be Solved by the Invention
The problem is that with the advance in high-capacity storage technologies, the word line Xi becomes an interconnection line having a great length with many memory cells connected thereto. As a result, the wiring capacity of the word line Xi becomes significant. In order to apply a high voltage to the word line Xi at high speeds, the P-channel transistor 780 is required to have the ability to adequately supply electric current to the word line Xi. This inevitably results in the increase in transistor size, which is counter to the need for large-scale integration of the non-volatile memory device that is needed with the advance in high-capacity storage technologies. In addition to this problem, another problem is that the increase in parasitic capacitance associated with the increase in transistor size interferes with the high-speed responsivity.
The large-sized P-channel transistor 780 also has a large gate capacitance, and the driver capacity of the predecoder (not shown) has to be increased to drive the gate of the P-channel transistor 780, which is also counter to the demand for large-scale integration of the non-volatile memory device needed for high-capacity storage technologies and which may also interfere with the high-speed responsivity.
In order to avoid the above-described problems, N-channel transistors each having a higher current drive capacity may be provided in place of the P-channel transistors 780 and 800. FIG. 11 shows a configuration of such arrangement. With reference to FIG. 11, there is also shown the bias relationship during the erase operation in which a negative bias is applied to a word line WL. N-channel transistors T1 and T2 are provided in place of the P-channel transistors 780 and 800 (Patent Document I).
Application of a negative bias (for example, −9 V) to the word line WL is made by supplying, after the level of a gate signal GWLB is rendered low (such as 0 V), a negative bias (for example, −9 V) to a source terminal XDS. At this time, a gate signal GWL of the N-channel transistor T1 is fed a negative bias of the same potential as the word line WL. In this case, a drain signal VWL is at a low level (such as 0 V). The N-channel transistor T1 is therefore biased to the electrically non-conductive state, and the gate-to-source voltage (VGS) thereof is 0 V.
With the advance in high-capacity storage technologies or for realization of high-speed access operations, it is necessary that the capacity to supply voltage to the word line WL be secured adequately while, on the other hand, there are restraints on transistor size because of the demand for improvement in the degree of integration. To cope with this inconsistency, the N-channel transistor T1 is employed, thereby securing adequate drive capabilities by miniaturization and by lowering of the threshold voltage. Consequently, there is the possibility that a leak current may flow even in a state of: VGS=0 V. In other words, a so-called tailing current may flow. The erase operation is carried out either for each sector which is a predetermined block within a memory cell array or for each sector group, and as high-capacity storage technologies advance, the number of in-sector word lines probably increases. Even if the tailing current flowing through an individual N-channel transistor T1 is a minute electric current, the negative bias of the word line WL may increase when the tailing current flows through many N-channel transistors T1. Since the capacity to supply negative bias generated from a positive voltage supply (such as a power supply voltage) depends on the performance of a charge pump circuit, there is the possibility that no predetermined negative voltage can be held for some types of inflow currents. In a memory cell of the non-volatile memory device in which an erase operation is carried out on the condition that a predetermined negative bias is applied, there is the possibility that with the rise in voltage value of the negative bias, the erase operation is left unfinished. Another possible problem is that normal data storage might not be assured. In addition, still another problem is that assurance of the capacity to absorb tailing current inevitably requires employment of a large scale configured charge pump circuit.
The provision of a FCER (Fast Chip Erase) mode or accelerator mode (ACC mode) as a function of simultaneously batch-erasing many sectors further increases the number of word lines WL that are supplied with negative bias voltages, thereby causing the tailing current to flow through a greater number of N-channel transistors T1. This results in the problem where it becomes more difficult to hold negative bias at a predetermined voltage level.